With the continuous increasing of the integration level of semiconductor devices, and the continuous decreasing of the technical node, the thickness of the conventional gate dielectric layer of the semiconductor devices has become smaller and smaller, but the leakage current of the gate electrode of a transistor has been increased. The increasing of the leakage current has caused certain issues including increasing the power consumptions, etc. In order to solve the leakage current issue and other related issues, a technique which uses a metal gate to substitute the conventional polysilicon gate has been developed. The gate structure having the metal gate and a high dielectric constant (high-K) gate dielectric layer is referred as a high-K metal gate (HKMG) structure. A gate-last process is a major process for forming the HKMG structure.
A process for forming a transistor with an HKMG structure includes providing a semiconductor substrate; and forming a dummy gate structure on the surface of the semiconductor substrate. The dummy gate structure includes a dummy gate dielectric layer formed on the surface of the semiconductor substrate; and a dummy gate electrode layer formed on the surface of the gate dielectric layer. The process also includes forming sidewall spacers on the side surfaces of the dummy gate structure; and forming an interlayer dielectric layer on the surface of the semiconductor substrate. The interlayer dielectric layer covers the surface of the semiconductor substrate and the side surface of the dummy gate structure; and the surface of the interlayer dielectric layer levels with the surface of the dummy gate structure.
Further, the process includes removing the dummy gate structure to form an opening; and sequentially forming a high-K dielectric layer, a work function layer, and a metal layer on the surface of the semiconductor substrate exposed by the opening. Further, the process also includes forming a stop layer; and planarizing the metal layer by a chemical mechanical polishing (CMP) process to form a metal gate.
Transistors having the HKMG structures are often formed in the core regions of the chip, such as logic regions, etc. Devices formed in the peripheral regions of the chip, such as the input/output regions, etc., still use polysilicon as the gate electrode material. Further, there are other device layers made of polysilicon or other materials are formed on the chip, such as polysilicon resistors, etc. When the CMP process is used to planarize the metal layer to form the metal gate, because the CMP process has a relative high polishing rate to polysilicon, etc., the device layers in other regions are often damaged by the CMP process; and certain defects, such as polishing dishes, etc., are formed on the top surface of the device layers; and contaminating residuals may be formed in the polishing dishes. Thus, the performance of the device layers may be affected. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.